Recently Intel's new Skylake-X platform changed cache hierarchy from a small L2 / big shared L3 to a big L2 / small shared L3. Considering this year Intel almost doubled the core count on its highest-end product, is this shift a technical compromise of scalability or a performance optimization?
Recently Intel's new Skylake-X platform changed cache hierarchy from a small L2 / big shared L3 to a big L2 / small shared L3. Considering this year Intel almost doubled the core count on its highest-end product, is this shift a technical compromise of scalability or a performance optimization?