I think as the transistor sizes became smaller, the resistance and capacitance went down, enabling higher clock rates. Interestingly, this also enabled more space on the die to fit more logic. Going parallel was the logical choice for the additional free space on the die after shrinking the transistors.
I think as the transistor sizes became smaller, the resistance and capacitance went down, enabling higher clock rates. Interestingly, this also enabled more space on the die to fit more logic. Going parallel was the logical choice for the additional free space on the die after shrinking the transistors.