I think the key part of this slide is: atomicity here means that "BusRD, BusRdx: no other bus transactions allowed between issuing address and receiving data". This ensures that when a cache control receives data, it is up-to-date, no other CPU might have changed the line.
Zarathustra
To elaborate: if you ask memory or another cache for some data, you won't have an issue where the data is read, then changed by another processor (before you receive the data), and then you get the (now stale) data.
I think the key part of this slide is: atomicity here means that "BusRD, BusRdx: no other bus transactions allowed between issuing address and receiving data". This ensures that when a cache control receives data, it is up-to-date, no other CPU might have changed the line.
To elaborate: if you ask memory or another cache for some data, you won't have an issue where the data is read, then changed by another processor (before you receive the data), and then you get the (now stale) data.