Previous | Next --- Slide 13 of 51
Back to Lecture Thumbnails

In a cache coherency model, we gain performance and mask latency using a write buffer. In the context of memory consistency, though the goal is to again mask latency from writes, we instead take advantage of instruction independence by re-ordering independent instructions. The bottleneck (memory latency) and end goal (performance) are the same between cache coherency and memory consistency, but the approaches are somewhat different.


We also have Snoop controller to reduce conflict and directory based cache coherence to utilize point to point message