Even in the uniprocessor case, there can be issues where the value of something in memory is not consistent with the value that is cached within the processor. Two examples are presented here that use Direct Memory Access (DMA) with a network card. In the first case, the processor sends the network a message by writing into a buffer in memory, and alerting the network card of the presence of the message. However, if the data for the message buffer was contained in the processor's cache, then all of the writes to the data processor will only be resident in the processor's cache, and they will not be visible in main memory, which is where the network card will read from. In the second example, the contents of the memory buffer that is accessible to the network card may be in the processor's cache, so when the network card writes to main memory, and alerts the CPU, nothing has happened to mark that cache line where the buffer data is as invalid, and as such data will be read from the cache, instead of from main memory, and as such, incorrect data will be read. Both of these issues show how a problem in coherence can still exist even if there is only one single processor. Essentially, for there to be a coherence problem, and assuming there is no cache coherence protocol in place, there must be at least two devices accessing--reading/writing--main memory. One type of solution to this problem exists by having shared regions of memory that cannot be cached--performed by the operating system.
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Cache coherence is an issue when different components connected to the memory hierarchy have different perceptions of what memory is at some certain time. A processor will include cache data in its perception of memory, an I/O device using DMA will not.
Even in the uniprocessor case, there can be issues where the value of something in memory is not consistent with the value that is cached within the processor. Two examples are presented here that use Direct Memory Access (DMA) with a network card. In the first case, the processor sends the network a message by writing into a buffer in memory, and alerting the network card of the presence of the message. However, if the data for the message buffer was contained in the processor's cache, then all of the writes to the data processor will only be resident in the processor's cache, and they will not be visible in main memory, which is where the network card will read from. In the second example, the contents of the memory buffer that is accessible to the network card may be in the processor's cache, so when the network card writes to main memory, and alerts the CPU, nothing has happened to mark that cache line where the buffer data is as invalid, and as such data will be read from the cache, instead of from main memory, and as such, incorrect data will be read. Both of these issues show how a problem in coherence can still exist even if there is only one single processor. Essentially, for there to be a coherence problem, and assuming there is no cache coherence protocol in place, there must be at least two devices accessing--reading/writing--main memory. One type of solution to this problem exists by having shared regions of memory that cannot be cached--performed by the operating system.
Cache coherence is an issue when different components connected to the memory hierarchy have different perceptions of what memory is at some certain time. A processor will include cache data in its perception of memory, an I/O device using DMA will not.