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acortes

Isn't it possible for 2 or more cores to request data from DRAM that would override each other in the L3 cache? I.e. core 1 and core 2 request a block of memory that maps into the same set and the same block? If this occurs then one of the two computations will be incorrect.

bpr

@acortes, If memory accesses from different cores map to the same cache set, it is no different than when a single core makes multiple accesses that conflict. The correctness is not affected, although the runtime can be.

gogogo

What determines the number of cache layers a processor uses? What benefits/costs do a high number of caches have over a lower number?

bpr

@gogogo, computer architects determine how many caches a processor will have based on extensive use of benchmarks and simulations. As you learned in 15-213/-513, there is a memory hierarchy where each layer can hold significantly more data, but is also slower to access that data. We will discuss some of the trade-offs this semester including those involving the design complexity of inclusive/exclusive caching and cache coherence. There are also the costs of using the transistors to make a cache versus another core or other component, and the power that the transistors require.