To ensure I understand the purpose of E, when we read we don't have to check if the memory has changed while in M we have to check that our line is not dirty, which takes some number of cycles.
bpr
@acortes, in the above diagram, each transition has two pieces X / Y. On X, the cache does Y and transitions accordingly. If the Y is --, then the cache does not need to do anything on the bus, which is preferred.
acortes
@bpr Then the benefit is that when we can reach M (via E) without doing the BusRdX when we transition from S to M?
bpr
@acortes, yes, if the cache line is in E, it can silently transition to M (i.e., do so without issuing a BusRdX).
Split_Personality_Computer
Can someone explain the purpose of flushing the data when another processor reads? I thought the point of these processor states is that once we've loaded in data from main memory we no longer have to communicate with main memory while we're processing that data with one of our cores.
bpr
@SPC, the S state will not flush the data, so any transition to S must flush. On a BusRdX, the question is whether the implementation supports a cache-to-cache transfer. If so, then the cache holding the line in M, just transfers the line in response to the BusRdX, otherwise, memory must supply the data.
To ensure I understand the purpose of E, when we read we don't have to check if the memory has changed while in M we have to check that our line is not dirty, which takes some number of cycles.
@acortes, in the above diagram, each transition has two pieces X / Y. On X, the cache does Y and transitions accordingly. If the Y is --, then the cache does not need to do anything on the bus, which is preferred.
@bpr Then the benefit is that when we can reach M (via E) without doing the BusRdX when we transition from S to M?
@acortes, yes, if the cache line is in E, it can silently transition to M (i.e., do so without issuing a BusRdX).
Can someone explain the purpose of flushing the data when another processor reads? I thought the point of these processor states is that once we've loaded in data from main memory we no longer have to communicate with main memory while we're processing that data with one of our cores.
@SPC, the S state will not flush the data, so any transition to S must flush. On a BusRdX, the question is whether the implementation supports a cache-to-cache transfer. If so, then the cache holding the line in M, just transfers the line in response to the BusRdX, otherwise, memory must supply the data.