For the mesif protocol i'm assuming that the first processor with a clean read gets put into the f state, while the subsequent reads from other processor are in the s state. Is this right?
bpr
@adilets, F migrates, so the most recent cache to request read permission receives the line in the F state, and sending the cache line downgrades the coherence state.
MangoSister
I have several questions regarding to the responsibility of transferring data:
1 In MESI/MESIF, say only one cache hold the data in M state, and then if another new processor request the data (either BusRd or BusRdX), the old cache must flush the data to memory. Does the new cache get data from memory after the old cache finishes flushing, or it get data from the old cache before flushing, or.. does flushing and supplying data to new cache happen simultaneously?
2 It seems that MOESI still does not solve the problem when there are multiple caches in S state but none in M state. Who should supply the data when there are only caches in S state (no M and thus no O)?
bpr
@MangoSister:
1) Yes, either. Since the S/F states are clean, the data must be written back to memory. It may also be possible to send the memory (or snoop from the bus) at that time.
2) With MESI, the design is to either have memory supply the data in the case with multiple S states, or the caches in S have to arbitrate who supplies the data. Usually if the design has O / F, then there is no arbitration step and the caches assume the O/F will handle supplying.
MangoSister
@bpr: (2) Yes I understand in MOESI, the cache in O state is supposed to supply the data. However, because O only comes from a previous M, a possible situation would be that there are multiple S, but no O. In such case, who should supply the data? (I think this won't happen in MESIF though because as you mentioned, the most recent cache to request read receives the line in F, so there must be one F in the same case.)
bpr
@MangoSister, "there is no arbitration step and the caches assume the O/F will handle supplying". So if no O (or no F) is present, then memory supplies the data.
While the most recent cache to issue a BusRd is in F, that does not guarantee that it will not evict the line before the the next BusRd for that line.
For the mesif protocol i'm assuming that the first processor with a clean read gets put into the f state, while the subsequent reads from other processor are in the s state. Is this right?
@adilets, F migrates, so the most recent cache to request read permission receives the line in the F state, and sending the cache line downgrades the coherence state.
I have several questions regarding to the responsibility of transferring data:
1 In MESI/MESIF, say only one cache hold the data in M state, and then if another new processor request the data (either BusRd or BusRdX), the old cache must flush the data to memory. Does the new cache get data from memory after the old cache finishes flushing, or it get data from the old cache before flushing, or.. does flushing and supplying data to new cache happen simultaneously?
2 It seems that MOESI still does not solve the problem when there are multiple caches in S state but none in M state. Who should supply the data when there are only caches in S state (no M and thus no O)?
@MangoSister: 1) Yes, either. Since the S/F states are clean, the data must be written back to memory. It may also be possible to send the memory (or snoop from the bus) at that time.
2) With MESI, the design is to either have memory supply the data in the case with multiple S states, or the caches in S have to arbitrate who supplies the data. Usually if the design has O / F, then there is no arbitration step and the caches assume the O/F will handle supplying.
@bpr: (2) Yes I understand in MOESI, the cache in O state is supposed to supply the data. However, because O only comes from a previous M, a possible situation would be that there are multiple S, but no O. In such case, who should supply the data? (I think this won't happen in MESIF though because as you mentioned, the most recent cache to request read receives the line in F, so there must be one F in the same case.)
@MangoSister, "there is no arbitration step and the caches assume the O/F will handle supplying". So if no O (or no F) is present, then memory supplies the data.
While the most recent cache to issue a BusRd is in F, that does not guarantee that it will not evict the line before the the next BusRd for that line.