When a processor is trying to gain exclusive access to the cache, it would need to broadcast its intent to every cache so that they can invalidate their local copies. How would hierarchical interconnects help make snooping-based cache coherence more scalable? In fact, wouldn't performance decrease when a processor has to broadcast its intent across multiple levels of indirection, as against using a shared interconnect?
llcoolj
In the top case, now data need not be broadcasted to 8 caches, but instead, a max of 4 caches. Yes performance might be worse for a singe cache controller; however, this will be more scalable for the overall hierarchy since there will be more, but smaller broadcasts
When a processor is trying to gain exclusive access to the cache, it would need to broadcast its intent to every cache so that they can invalidate their local copies. How would hierarchical interconnects help make snooping-based cache coherence more scalable? In fact, wouldn't performance decrease when a processor has to broadcast its intent across multiple levels of indirection, as against using a shared interconnect?
In the top case, now data need not be broadcasted to 8 caches, but instead, a max of 4 caches. Yes performance might be worse for a singe cache controller; however, this will be more scalable for the overall hierarchy since there will be more, but smaller broadcasts