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amolakn

In this example you chose to dedicate 1% of the chip area to the rasterizer which was non ideal. In the real world, how exactly do they determine how much of a chip area to dedicate to different tasks? Is it just with testing and trial and error to figure out which ones will require the most CPU power so that there isn't this sort of bottleneck?

neonachronism

I imagine they use significant simulation, given the high costs involved in fabing a new design (and bringing it to a reasonable yield). Also, since Intel's floating point errors in the 90's, there's some amount of formal verification going on (although its for correctness, not efficiency).