I don't quite understand the P^2. Once the processor gives up its lock, this forces an invalidation by all other processors. Then shouldn't there only be one more invalidation caused by the first processor to get the lock? (Why wouldn't the other processors see that the lock is taken again and therefore not try?)
bpr
@Holladay, all the processors have been invalidated by the write operation releasing the lock. Next, they all read the cache line again, placing these requests on the bus or to the directory. The first processor receives the data and sees that the lock has been released, thereby issuing the test-and-set and requesting write permission. However, at the same time, many other processors will also be receiving the cache line and making the same decision. Even if the write invalidation is seen, those processors have to be able to complete their read before the write happens. Therefore, all of the processors issuing the read before the write will also attempt to write to the cache line. Then, while those failing writes (i.e., not acquiring the lock) are taking place, the earlier failed writes are switching to read requests of the cache line. Eventually the system will be quiescent as the processors spin in their read loop.
The key thing is that a processor will make progress on a memory operation even if another processor's request will remove the required permissions.
I don't quite understand the P^2. Once the processor gives up its lock, this forces an invalidation by all other processors. Then shouldn't there only be one more invalidation caused by the first processor to get the lock? (Why wouldn't the other processors see that the lock is taken again and therefore not try?)
@Holladay, all the processors have been invalidated by the write operation releasing the lock. Next, they all read the cache line again, placing these requests on the bus or to the directory. The first processor receives the data and sees that the lock has been released, thereby issuing the test-and-set and requesting write permission. However, at the same time, many other processors will also be receiving the cache line and making the same decision. Even if the write invalidation is seen, those processors have to be able to complete their read before the write happens. Therefore, all of the processors issuing the read before the write will also attempt to write to the cache line. Then, while those failing writes (i.e., not acquiring the lock) are taking place, the earlier failed writes are switching to read requests of the cache line. Eventually the system will be quiescent as the processors spin in their read loop.
The key thing is that a processor will make progress on a memory operation even if another processor's request will remove the required permissions.
@bpr Thank you for the detailed explanation!