Here it says there is "Cache miss of line X". So in each iteration of interleavely fetch the bytes from 8 chips, it seems it is always cache miss ? While if we fetch the whole line of the first chip, then there are some cache hit to be expected.
Not sure if I was on the right track here.
lusiliang93
I think since cache miss of line X happens in LLC,we need to read the data from memory by using memory controller. Interleaved address space allows higher throughput. Is there any specific reason why a DRAM usually has 8 pins?
One question come up while reviewing:
Here it says there is "Cache miss of line X". So in each iteration of interleavely fetch the bytes from 8 chips, it seems it is always cache miss ? While if we fetch the whole line of the first chip, then there are some cache hit to be expected.
Not sure if I was on the right track here.
I think since cache miss of line X happens in LLC,we need to read the data from memory by using memory controller. Interleaved address space allows higher throughput. Is there any specific reason why a DRAM usually has 8 pins?