I think it's interesting that simply adding a second channel we can improve throughput. Does this mean that the memory is equivalent between channel 0 and channel 1? Is having a dual channel useful if there is instruction level parallelism where multiple load/store instructions are occurring at the same clock cycle?
yey1
I don't think the memory in channel 0 and 1 are equivalent. DRAM is not cheap, for me it doesn't make sense to duplicate memory.
anamdev
@yey1 That does make sense. Then for a followup, does dual channel show improvement in latency when
a) 2 processors are trying to the different memory locations
b) there happens to be ILP in a single processor where there are multiple memory instructions that requires the use of both memory controllers
bpr
@anamdev and @yey1, when adding channels, we are splitting the DRAM between the channels. With two channels, perhaps the low half of physical addresses are on channel 0 and the high half on channel 1, or perhaps they are interleaved, or .... Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging is a recent work that explores more dynamic approaches to making these mapping decisions.
Even without ILP, there is still benefit to MLP (memory-level-parallelism). This slide does not show the probable fact that the "CPU" is actually a multi-core processor and there would be many memory requests from the different cores all contending for the channel(s). Also you should remember how the consistency model impacts how a single core can issue multiple memory requests.
carnegieigenrac
I'm interested in the decision to have a design with 2 memory controllers as opposed to just increasing the number DRAM chips per controller. Is the number of 8 DRAM chips per controller just arbitrarily chosen for these slides, or is there actually a significant reason why memory controllers are just limited to 8 chips? I'd guess that increasing the number of DRAMs per controller makes the controller exponentially more complex - is this correct?
I think it's interesting that simply adding a second channel we can improve throughput. Does this mean that the memory is equivalent between channel 0 and channel 1? Is having a dual channel useful if there is instruction level parallelism where multiple load/store instructions are occurring at the same clock cycle?
I don't think the memory in channel 0 and 1 are equivalent. DRAM is not cheap, for me it doesn't make sense to duplicate memory.
@yey1 That does make sense. Then for a followup, does dual channel show improvement in latency when a) 2 processors are trying to the different memory locations b) there happens to be ILP in a single processor where there are multiple memory instructions that requires the use of both memory controllers
@anamdev and @yey1, when adding channels, we are splitting the DRAM between the channels. With two channels, perhaps the low half of physical addresses are on channel 0 and the high half on channel 1, or perhaps they are interleaved, or .... Improving DRAM Bandwidth Utilization with MLP-Aware OS Paging is a recent work that explores more dynamic approaches to making these mapping decisions.
Even without ILP, there is still benefit to MLP (memory-level-parallelism). This slide does not show the probable fact that the "CPU" is actually a multi-core processor and there would be many memory requests from the different cores all contending for the channel(s). Also you should remember how the consistency model impacts how a single core can issue multiple memory requests.
I'm interested in the decision to have a design with 2 memory controllers as opposed to just increasing the number DRAM chips per controller. Is the number of 8 DRAM chips per controller just arbitrarily chosen for these slides, or is there actually a significant reason why memory controllers are just limited to 8 chips? I'd guess that increasing the number of DRAMs per controller makes the controller exponentially more complex - is this correct?