Cache misses can't always be improved though, correct? Isn't it possible that for some problem maybe the best we can do is a 24% miss rate? Doesn't it just depend how the problem forces you to access your memory?
Cache misses can't always be improved though, correct? Isn't it possible that for some problem maybe the best we can do is a 24% miss rate? Doesn't it just depend how the problem forces you to access your memory?