Since Shared and Dirty state is maintained per cache line, how do these 3 bus wires suffice to preserve the appropriate state of every line in the cache?
Tengjiao
First, the state of each cache line is maintained in each cache line.
Second, for a snoopy-based protocol, bus is shared.
Third, those three wires are for communication purpose. Say I have a read miss, I send the request on Addr bus. Then I check snoop-pending. When everyone checks its results, then I will check if Shared and Dirty is up
Nothing up --> I read it from memory as EXCLUSIVE shared state
Shared up --> I read it as shared state
Dirty up --> I read it from the dirty cache line as shared state
Since Shared and Dirty state is maintained per cache line, how do these 3 bus wires suffice to preserve the appropriate state of every line in the cache?
First, the state of each cache line is maintained in each cache line.
Second, for a snoopy-based protocol, bus is shared.
Third, those three wires are for communication purpose. Say I have a read miss, I send the request on Addr bus. Then I check snoop-pending. When everyone checks its results, then I will check if Shared and Dirty is up
Nothing up --> I read it from memory as EXCLUSIVE shared state Shared up --> I read it as shared state Dirty up --> I read it from the dirty cache line as shared state