In this slide, we see a state diagram representing a simple cache coherence protocol (it assumes write-through, no-allocate caches). The cache line can be said to be in either one of two states: valid (dirty bit is not set) or invalid (dirty bit set).

Assuming we start in the invalid state, upon issuing a processor write, the cache line stays in the invalid state, as the write is made directly to memory (no-allocate policy). Seeing a write from another processor will result in a cache line in the valid state to transition to invalid state. The cache "drops" its line so that on the next read, it will observe the updated result.

A read or write, however, will result in a transition into the valid state.

This comment was marked helpful 0 times.

@Amanda: Everything you described is true except for the part of about the dirty bits. This is a write-through cache... so there's no concept of a dirty line. The writes always immediately propagate to memory. There are no dirty bits for cache lines, just valid and invalid states!

Also, I believe you mean "cache line" when you write "we" in paragraph two.

This comment was marked helpful 0 times.

Question: Why does a processor need to send a BusRd when it performs PrRd in invalid state?

This comment was marked helpful 0 times.

@Mayank You need to do a BusRd because you need to load the data from main memory, since your local version is invalid.

This comment was marked helpful 0 times.