Another reason that a larger line size might hurt is that if your program has poor locality increasing cache line size effectively makes your cache smaller by reducing the number of items that can be stored in your cache.
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Mayank
Here is an example of how increasing line size can reduce the number of true sharing coherence misses when spatial locality is present:
Lets assume processors P1 and P2 share an array X[8]. Also, assume a cache line can store 4 elements of X. P1 writes to all elements of X[8] (spatial locality assumption). This leads P2 to invalidate 2 cache lines. Now when P2 wishes to read elements of X, there will be 2 "true sharing coherence misses".
If the cache line was double (could store 8 instances of X), then P2 would have just incurred one "true sharing coherence miss".
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markwongsk
Question: although "false sharing" was defined in the previous lecture, I don't recall seeing the terminology "true sharing". I presume this just means that the processors are writing to the same memory addresses (as opposed to false sharing where the processors write to different memory addresses)?
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Xelblade
@markwongsk Yeah, true sharing refers to when actual sharing of data is necessary. I believe we mentioned it in class.
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tpassaro
Would prefetching be considered an improvement to decrease the cache miss rate? I think this would fall under the compilers job, it still might be useful. Also, having too small of cache lines can lead to more misses. For instance, if you are iterating through an array of integers, and your cache line only has room for 2 contiguous integers. Each time you have an integer list larger than 2, you incur a cache miss on every third integer.
Another reason that a larger line size might hurt is that if your program has poor locality increasing cache line size effectively makes your cache smaller by reducing the number of items that can be stored in your cache.
This comment was marked helpful 0 times.
Here is an example of how increasing line size can reduce the number of true sharing coherence misses when spatial locality is present:
Lets assume processors P1 and P2 share an array
X[8]. Also, assume a cache line can store 4 elements ofX. P1 writes to all elements ofX[8](spatial locality assumption). This leads P2 to invalidate 2 cache lines. Now when P2 wishes to read elements ofX, there will be 2 "true sharing coherence misses".If the cache line was double (could store 8 instances of
X), then P2 would have just incurred one "true sharing coherence miss".This comment was marked helpful 2 times.
Question: although "false sharing" was defined in the previous lecture, I don't recall seeing the terminology "true sharing". I presume this just means that the processors are writing to the same memory addresses (as opposed to false sharing where the processors write to different memory addresses)?
This comment was marked helpful 0 times.
@markwongsk Yeah, true sharing refers to when actual sharing of data is necessary. I believe we mentioned it in class.
This comment was marked helpful 0 times.
Would prefetching be considered an improvement to decrease the cache miss rate? I think this would fall under the compilers job, it still might be useful. Also, having too small of cache lines can lead to more misses. For instance, if you are iterating through an array of integers, and your cache line only has room for 2 contiguous integers. Each time you have an integer list larger than 2, you incur a cache miss on every third integer.
This comment was marked helpful 0 times.