Xeon7350 works at 2.93GHz and it has 4 cores. This is how the instructions/sec in millions reached beyond 10^6, which is un-realistic in single core CPU.
Question: what does the red line mean? There seems be some processors (dots in the graph) working at around 10^9 instructions/sec with relatively small instruction joule. But the line is high above these.
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chenc3
I guess the red line is the upper bound of the instruction per J we can get for a given frequency.
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edwardzh
The reason why Ghz is not free (in terms of power) is that we have reached a limit with continued Dennard scaling, the idea that as transistors get smaller the power density stays the same.
Interestingly, many people are also of the opinion that parallelism is also not free - nowhere close to free. Because of limited parallelism, these people predict another so-called wall: dark silicon, where much of a multi-core chip is powered off (due to lack in parallelism, excessive heterogeneity, or even due to power limitations) at any given point, and the percent that is powered off increases with the increase in number of cores.
Xeon7350 works at 2.93GHz and it has 4 cores. This is how the instructions/sec in millions reached beyond 10^6, which is un-realistic in single core CPU.
Question: what does the red line mean? There seems be some processors (dots in the graph) working at around 10^9 instructions/sec with relatively small instruction joule. But the line is high above these.
This comment was marked helpful 0 times.
I guess the red line is the upper bound of the instruction per J we can get for a given frequency.
This comment was marked helpful 0 times.
The reason why Ghz is not free (in terms of power) is that we have reached a limit with continued Dennard scaling, the idea that as transistors get smaller the power density stays the same.
Interestingly, many people are also of the opinion that parallelism is also not free - nowhere close to free. Because of limited parallelism, these people predict another so-called wall: dark silicon, where much of a multi-core chip is powered off (due to lack in parallelism, excessive heterogeneity, or even due to power limitations) at any given point, and the percent that is powered off increases with the increase in number of cores.
This comment was marked helpful 0 times.