Am i correct in understanding that it's the fetch/decode unit that's responsible for the instruction stream? So for ILP, we require multiple fetch/decode units as the instructions being executed in parallel can be different, while in case of SIMD architecture, it's just one fetch/decode unit passing along the same instruction to all ALUs...
althalus
@sidwad, yes i think that is the case as shown in the next 2 slides with more decoder units
Am i correct in understanding that it's the fetch/decode unit that's responsible for the instruction stream? So for ILP, we require multiple fetch/decode units as the instructions being executed in parallel can be different, while in case of SIMD architecture, it's just one fetch/decode unit passing along the same instruction to all ALUs...
@sidwad, yes i think that is the case as shown in the next 2 slides with more decoder units