Parallel Computer Architecture and Programming (CMU 15-418/618)

This page contains practice exercises to help you understand material in the course. Reference material and lecture videos are available on the Lectures page.

Self-Check Exercises

Exercise 1: A Task Queue on a Multi-Core, Multi-Threaded CPU
Concepts tested: multi-core architecture, hardware multi-threading

Exercise 2: Data-Parallel Histograms, and the Prof. Kayvon Processing Unit (PKPU)
Concepts tested: multi-core architecture, hardware multi-threading, data-parallel algorithms, abstraction vs. implementation

Exercise 3: More on Histograms, Angry Students
Concepts tested: cache coherence, performance optimization

Exam 1 Practice Exercises
Concepts tested: everything up to Exam 1

Exercise 4: Good Business Practices, Understanding Load-linked, Store-conditional
Concepts tested: elastic scheduling, implementing synchronization, review of cache coherence and latency hiding

Exercise 5: Concurrent Linked Lists and Heaps
Concepts tested: fine-grained locking and transactional memory

Exercise 6: Justin, Kanye and Taylor Bring Locality Back, Controlling DRAM
Concepts tested: scheduling Spark programs, how DRAM works

Exam 2 Practice Exercises
Concepts tested: everything from the memory consistency lecture onward

Programming Assignments

Assignment 1: Analyzing Parallel Program Performance on a Quad-Core CPU

Assignment 2: A Simple Renderer in CUDA

Assignment 3: ParaGraph: A Parallel Graph Library on Xeon Phi

Assignment 4: A Simple, Elastic Web Server