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Add details of some units:

The retirement unit writes the results of speculatively executed microoperations into the user-visible registers and removes the microoperations from the reorder buffer. Like the reservation station, the retirement unit continuously checks the status of microoperations in the reorder buffer, looking for ones that have been executed and no longer have any dependencies with other microoperations in the instruction pool. It then retires completed microoperations in their original program order.

The memory interface unit handles load and store microoperations.

Branch target buffers (BTBs) are caches in which branch information is stored that is used for branch prediction by the fetch stage of the instruction pipeline.


Just to add additional detail for those interested:

The Complex Instruction Decoder and Microcode Instruction Sequencers are one of the more interesting units. While the modern x86 and x86-64 ISA's are CISC, many of the instructions in the ISA would be extremely difficult to implement as is. Take rep movsb, which is how memset is implemented. This copies a byte continuously to a memory destination. The way this is implemented on modern processors is through a microcode program. A microcode program is a series of micro-instructions (instructions that explicitly define all of the control signals for the processor) stored in ROM. For rep movsb, the microcode program implements a loop where the byte is continuously stored into ascending memory locations.

The Memory Reorder Buffer is used to service memory requests for the Out-of-Order engine. I imagine this will be something mentioned in later lectures, as it effects memory consistency. The memory reorder buffer is used to hold and service memory requests from the processor. While the requests are dispatched (sent out) in the program order, they do not necessarily complete in program order. The Memory Reorder Buffer is responsible for determining what order requests can complete in, and as well as allowing the reordering of certain requests by allowing completed accesses to be reported to the processor out of program order. Current x86 processors use a total store ordering (TSO) memory model. In this model, the only memory accesses that can be reordered are loads that occur after but complete before an earlier store. All other memory accesses are forced into program order.