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I highly recommend you read Sorin, Hill, and Wood's Primer on Memory Consistency and Cache Coherence. It's a very nice discussion of the issues in this lecture, and previous lectures on cache coherence.


For a parallel system (with caches) to have some memory consistency, it must also be cache coherent?


Not necessarily, memory consistency and cache coherence are two orthogonal concepts, so each can be implemented independently on a system. Memory consistency deals with the relative ordering of memory operations to separate memory locations, while cache coherence deals the relative ordering to the same memory location.

Actually, implementing consistency is simpler in general then cache coherence, because consistency is implemented independently on each processor, whereas coherence requires a fair bit of inter-processor communication. However, in practice, a system without cache coherence is quite rare, so I'm not familiar with any real systems that have some memory consistency, but no cache coherence.


@bmperez Actually, sequentially consistent implies coherent. I am able to find a proof here: The main point is, coherence implies the order of accesses to an individual memory location while consistency refers to the order of accesses to all memory locations, so we cannot have consistency without coherence, IMO.


X memory address : a -> b -> c

Y memory address : d -> e -> f

Memory coherent only ensure the sequential in one memory address, while consistency ensure the sequence across the memory address.

If X: abc and Y: def doesn't necessarily guarantee the sequence "abcdef", it could any order "abdecf" or "abdefc"... just like any race condition we have seen before.