As said in class,
Writeback buffer for cache is a buffer to delay the flush of writes that have already happened to memory. If there was no cache, there would be no need for a writeback buffer.
Write buffer is used to delay the writes itself.
What I found to be a big takeaway was that the write buffer is for between the processor and the cache, and the write-back buffer is for between the cache and memory. That really helped me.
Write buffer contains data from a write that is not committed yet (not ever appear on bus), write-back buffer contains data from a write that is committed but not completed (not flushed to memory).
How to understand this WR reorder? It seems that the order of issuing read/write is not changed. What is changed is just the order of executing them. In my previous understanding, the read/write reorder should be like the instructions are issued unordered (those super scaler processors).
So just to visualize this a little bit better, would the write buffer be placed in between the processor and the write-back buffer?
You could say so.
When is the write buffer flushed? When any processor issues a read at the address of the value stored in the write buffer?
@MaxFlowMinCut, I think it hard to predict "when". It all depends the speed of write operation.
@arcticx, because the W is not finished processing when R is issued with write buffer.