Allowing reads before writes allows better performance over time and allows the write latency to be hidden. TSO Gives the guarantee that all processors have to see a write before any processor that did not do the write can see it. PC has no such guarantees
ZhuansunXt
Maybe this implies that PC may be more preferred in a NUMA (Non-uniform memory access) system, since some processor will require longer time to observe the newly written value.
kayvonf
Although memory consistency and cache coherence are two different things, it's certainly true that the implementation of cache coherence may dictate what consistency model a memory system provides.
For example, consider the implementation of invalidation-based cache, coherence, where the main idea is that a cache must obtain a line in an exclusive-for-write state (e.g., MSI, MESI's "M" state), prior to a write. Since the write waits for acknowledgment from all processors that they have dropped the line, you have write atomicity -- it's not possible for one cache to observe a write and another not. (hence, you're not going to have PC memory consistency in a system implemented invalidation-based cache coherence.)
xiaoguaz
From wiki, I notices that processor consistency will require cache coherence. However, which kind of cache coherence will lead to processor consistency?
PandaX
I think TSO can be viewed as a more strict form of relaxed memory system.
althalus
For processor consistency, if any processor can read the value of A before the write is observed by all processors, how do you ensure that the processor reading it has the new value not the stale value?
jsunseri
@althalus I think the programmer would have to decide that read/write ordering is important for a particular set of instructions and use a memory barrier. This would insure that the value of A that is read is the one that was previously written according to the sequential ordering of the program.
monkeyking
Same question as althalus. I think it should be "... can read value of A ..." instead of "... can read new value of A ..."
xiaoguaz
@althalus @monkeyking I think PC cannot assure one processor read the value is newest value before the write is observed by all processors. As for TSO, one processor can always read the old value the write is observed by all processors.
Lawliet
So from what I understand, anything that TSO can observe, PC can observe because PC is a more strict version of TSO.
traveling_saleswoman
@Lawliet Actually, PC is a more relaxed version of TSO because it relaxes TSO's second requirement, that other processors can't read A until any writes to A are observed by all processors.
Allowing reads before writes allows better performance over time and allows the write latency to be hidden. TSO Gives the guarantee that all processors have to see a write before any processor that did not do the write can see it. PC has no such guarantees
Maybe this implies that PC may be more preferred in a NUMA (Non-uniform memory access) system, since some processor will require longer time to observe the newly written value.
Although memory consistency and cache coherence are two different things, it's certainly true that the implementation of cache coherence may dictate what consistency model a memory system provides.
For example, consider the implementation of invalidation-based cache, coherence, where the main idea is that a cache must obtain a line in an exclusive-for-write state (e.g., MSI, MESI's "M" state), prior to a write. Since the write waits for acknowledgment from all processors that they have dropped the line, you have write atomicity -- it's not possible for one cache to observe a write and another not. (hence, you're not going to have PC memory consistency in a system implemented invalidation-based cache coherence.)
From wiki, I notices that processor consistency will require cache coherence. However, which kind of cache coherence will lead to processor consistency?
I think TSO can be viewed as a more strict form of relaxed memory system.
For processor consistency, if any processor can read the value of A before the write is observed by all processors, how do you ensure that the processor reading it has the new value not the stale value?
@althalus I think the programmer would have to decide that read/write ordering is important for a particular set of instructions and use a memory barrier. This would insure that the value of A that is read is the one that was previously written according to the sequential ordering of the program.
Same question as althalus. I think it should be "... can read value of A ..." instead of "... can read new value of A ..."
@althalus @monkeyking I think PC cannot assure one processor read the value is newest value before the write is observed by all processors. As for TSO, one processor can always read the old value the write is observed by all processors.
So from what I understand, anything that TSO can observe, PC can observe because PC is a more strict version of TSO.
@Lawliet Actually, PC is a more relaxed version of TSO because it relaxes TSO's second requirement, that other processors can't read A until any writes to A are observed by all processors.