Following PSO, the program may now print 1 or 0 compared to the case of TSO where it can only print 1. Printing 0 can happen because writes can now be reordered, and so if the flag gets set to 1 and thread 2 executes before A is set to 1, then print A results in 0.
colorblue
Im confused how the execution may not match sequential consistency and this still be considered a valid model. Does this just mean more of the burden is placed on the compiler and the programmer in order to avoid consistency problems. I know the professor mentioned that most memory systems are relaxed and I was personally unaware of this. Is the work done to keep it sequential very advanced at this point that it is better that the programmer does not have to worry about the implementation?
fleventyfive
@colorblue, I believe so, yes. I think that making programmers take care of memory consistency is extremely dangerous, which is why even if the underlying system has a relaxed consistency model, then some part of the system up the stack (OS, compiler, etc.) will handle it for us.
And yes, as Prof. Kayvon mentioned, if no module up the stack does this for the programmer, then the programmer will have to add fences in his code to ensure sequential consistency, just like the question on the exam 1.
leis1
In case someone is here and wonder:
TSO and PC allows W->R reordering to hide write latency.
Difference is that TSO guarantees that when processor write to A, the new A value to be visible to other processors at the same time. In PC, some processor could see the new A while others only see the old A (not including the the processor who writes to A in the first place).
PS allows W->W reordering. In other words, processor P write to A first and then write to B. new B might be visible before new A becomes visible. (There's no clarification in slides about does the new value has to be visible to all other processors at the same time but I think you can assume a yes)
huehue
Does PSO have the same rules as TSO or PC for W->R reordering? Does a write have to be observed by all processors before a processor can read the new value?
Following PSO, the program may now print 1 or 0 compared to the case of TSO where it can only print 1. Printing 0 can happen because writes can now be reordered, and so if the flag gets set to 1 and thread 2 executes before A is set to 1, then print A results in 0.
Im confused how the execution may not match sequential consistency and this still be considered a valid model. Does this just mean more of the burden is placed on the compiler and the programmer in order to avoid consistency problems. I know the professor mentioned that most memory systems are relaxed and I was personally unaware of this. Is the work done to keep it sequential very advanced at this point that it is better that the programmer does not have to worry about the implementation?
@colorblue, I believe so, yes. I think that making programmers take care of memory consistency is extremely dangerous, which is why even if the underlying system has a relaxed consistency model, then some part of the system up the stack (OS, compiler, etc.) will handle it for us. And yes, as Prof. Kayvon mentioned, if no module up the stack does this for the programmer, then the programmer will have to add fences in his code to ensure sequential consistency, just like the question on the exam 1.
In case someone is here and wonder:
TSO and PC allows W->R reordering to hide write latency.
Difference is that TSO guarantees that when processor write to A, the new A value to be visible to other processors at the same time. In PC, some processor could see the new A while others only see the old A (not including the the processor who writes to A in the first place).
PS allows W->W reordering. In other words, processor P write to A first and then write to B. new B might be visible before new A becomes visible. (There's no clarification in slides about does the new value has to be visible to all other processors at the same time but I think you can assume a yes)
Does PSO have the same rules as TSO or PC for W->R reordering? Does a write have to be observed by all processors before a processor can read the new value?
@huehue Check out http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-95-7.pdf especially Figure 8 and section 6.3. Looks like PSO has the same rules as TSO with respect to atomicity requirements.