In directory, P presence bits indicate which processors hold the cache line in caches. Dirty bit indicates whether a line is dirty in one of the processors' caches. In this slide, how does processor 1 know whose owner id should it send to processor 0 as response? It seems to me that neither presence bits nor dirty bit has this information.
althalus
@haboric, I assume that if the dirty bit is set, this means that only one of the other processors has the data in its cache to which it will write to. If multiple presence bits have been set, it should mean that those processors have the data as read only since to be able to write, we still need the processor to have exclusive access, or do we(I am assuming this)?
mallocanswer
I'm a little confused here. Why should the directory of processor 1 need to keep track of the ownership of the content? It doesn't own the content in its memory.
Fantasy
@mallocanswer
Processor 1 keeps track of the ownership of the content because it is the homenode of the content. In addition, I think the present bit of p1 is 0 because processor 2 is having exclusive access to that data (dirty bit is 1).
cyl
Isn't the dirty bit means the exclusive access here? What's the relation with source another processor?
mallocanswer
@cyl, dirty bit here means processor 2 exclusively owns the data. Not quite understand what you mean by "source another processor".
cyl
I think I get it. The third presence bit indicates that the cache line is in processor 2, the dirty bit means it's the exclusive line. So it has to go to the third processor for the data.
mallocanswer
@cyl, the third presence bit only indicates processor 2 has the data in its cache. However, the third presence bit with dirty bit can tell other processors processor 2 has most updated data.
In directory, P presence bits indicate which processors hold the cache line in caches. Dirty bit indicates whether a line is dirty in one of the processors' caches. In this slide, how does processor 1 know whose owner id should it send to processor 0 as response? It seems to me that neither presence bits nor dirty bit has this information.
@haboric, I assume that if the dirty bit is set, this means that only one of the other processors has the data in its cache to which it will write to. If multiple presence bits have been set, it should mean that those processors have the data as read only since to be able to write, we still need the processor to have exclusive access, or do we(I am assuming this)?
I'm a little confused here. Why should the directory of processor 1 need to keep track of the ownership of the content? It doesn't own the content in its memory.
@mallocanswer Processor 1 keeps track of the ownership of the content because it is the homenode of the content. In addition, I think the present bit of p1 is 0 because processor 2 is having exclusive access to that data (dirty bit is 1).
Isn't the dirty bit means the exclusive access here? What's the relation with source another processor?
@cyl, dirty bit here means processor 2 exclusively owns the data. Not quite understand what you mean by "source another processor".
I think I get it. The third presence bit indicates that the cache line is in processor 2, the dirty bit means it's the exclusive line. So it has to go to the third processor for the data.
@cyl, the third presence bit only indicates processor 2 has the data in its cache. However, the third presence bit with dirty bit can tell other processors processor 2 has most updated data.