Question: After step 5, shouldn't presence[1] in Node 1 be set?
hofstee
@BensonQiu Why? It's not in Processor 1's cache.
Khryl
What will happen if processor 1 also has this line outdated in cache? In step 5, will its presence bit be set to 1, and its cache line also updated with data from processor 2?
haboric
@Khryl I think so.
arcticx
Step 3, why requesting data from owner and then owner update the home node in step 5? Why not let the owner update the home node first and then from home node send the updated value to requesting node. This way, the requesting node will not need to communicate with 2 different nodes, and the total communication times will also decrease by 1.
kayvonf
@articx: Yep, that's an optimization that reduces the number of messages sent, but not the total latency of the operation. We discuss it specifically later in this lecture.
kayvonf
@Kryl: "What will happen if processor 1 also has this line outdated in cache?" Why would an invalidation-based coherence protocol prevent the situation you suggestion from happening? You seem to be saying: what if a line was dirty and writable in one cache and also in another cache but stale?
Khryl
@kayvonf, Ah I see, it can never happen because when a line in one cache move to M state, it will invalidate the line in other caches. Only one cache can be in M state.
Question: After step 5, shouldn't presence[1] in Node 1 be set?
@BensonQiu Why? It's not in Processor 1's cache.
What will happen if processor 1 also has this line outdated in cache? In step 5, will its presence bit be set to 1, and its cache line also updated with data from processor 2?
@Khryl I think so.
Step 3, why requesting data from owner and then owner update the home node in step 5? Why not let the owner update the home node first and then from home node send the updated value to requesting node. This way, the requesting node will not need to communicate with 2 different nodes, and the total communication times will also decrease by 1.
@articx: Yep, that's an optimization that reduces the number of messages sent, but not the total latency of the operation. We discuss it specifically later in this lecture.
@Kryl: "What will happen if processor 1 also has this line outdated in cache?" Why would an invalidation-based coherence protocol prevent the situation you suggestion from happening? You seem to be saying: what if a line was dirty and writable in one cache and also in another cache but stale?
@kayvonf, Ah I see, it can never happen because when a line in one cache move to M state, it will invalidate the line in other caches. Only one cache can be in M state.