Previous | Next --- Slide 48 of 51
Back to Lecture Thumbnails

To pass data around this 512 bit ring (bus) I assume there should be some bus-master, right? I assume there is bus arbitration involved which makes it sort of intuitive how the data is passed on this ring. But I am not able to think of what sort of arbitration happens in the next-gen Xeon (on the next slide) which has a mesh based interconnection.

Can somebody point to some good reading?


The ring is not a bus. It is the topology of the on-chip network. We will cover this topic in class in more detail after Spring Break.

If you are an ACM student member, you can read "Principles and Practices of Interconnection Networks" for free,


To put it another way, the ring is comprised of a ring of connected cores. Each core is connected to the cores adjacent to it on the ring. The choice to arrange processors in a ring like this involves the trade-off between space used to handle communication (maximum with a cross-bar which connects all processors to all other processors). This is one of the simplest ways to connect cores, but requires more hops to send between processors far from one another on the ring.