Previous | Next --- Slide 42 of 47
Back to Lecture Thumbnails

As mentioned in lecture, one of the big potential advantages of FGPAs is that they'll allow chip manufacturers to have a little bit more breathing room in regards to how much of the chip they partition to hardware level logic (currently ASIC) vs. normal execution units. Currently, chip producers have to be a bit conservative and over-provision the fixed-function components on the chip because it could severely negatively affect the efficiency of the chip if the ASIC parts of the chip are bottlenecks; during which times a huge proportion of the chip is sitting idle.


To elaborate on what diminishing their advantage means, kayvon in lecture mentioned how by over-provisioning(providing more specialized chips than needed), the efficiency of heterogeneous system decreases, because in most cases, many of these chips will be left idle.


I am quite confused about How is the 1.2% and 80% number calculated?


@yikesaiting Currently 1% of chip area is used for rasterizer, which is under-provision and need 20% more throughput. In order to reach max throughput we have to dedicate 1.2% of chip area used for rasterizer.

Since the other 99% of the chip are waiting for the result of rasterization, if rasterization is 20% slower than it should be the other part can only work at 80% efficiency.


Why couldn't there be a general purpose part of the chip (say 10%) that might be slower but usable for anything? Then we could also rasterize on that part and even if it needs all 5% of the general purpose part to finish at the same time as the rasterizer, the entire chip won't be slowed down by 20% (it might be slowed down by a bit less)?

I imagine one of the challenges of this is knowing how to put work that is compiled for the rasterizer onto something more general purpose.