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Prof. @kayvonf mentioned if the charge is 0, it "spreads out"...can someone please explain this concept? Also, if I understand it correctly, the steps for a DRAM operations are:

(1) Have a baseline voltage running through all columns.

(2) Go to the location of the byte you want to read and activate that row (highlighted by red in this case).

(3) I am not quite sure about this one but I think this one is basically selecting the columns where the data is present in.

(4) Transfer data to the bus.

(5) Bus transfers the byte in a single clock cycle


Precharge and row activation are not needed if we need a byte form an already activated row. Spatial locality matters.


It would be interesting to see a comparison between the contribution of DRAM reads and cache hits to the performance consequence of lacking spatial locality. Which one has a more negative impact on latency when spatial locality is absent/lacking?