Does this setup essentially allow two PRE, RAS and CAS requests to occur at the same time?
Dual channel memory typically works best if the memory modules match in capacity, speed, latency, number of chips, and number of rows+cols.
Ok, so this is different from having banks. Banks allow pipelining of memory accesses on one DRAMS, whereas having multiple memory controllers simply doubles the speed?
@pavelkang I think it doubles the throughput instead of latency (speed)