How does hardware avoid this problem at the cache level. For example, if two processors both have the same memory address in their L1 cache and are reading from and writing to it concurrently, how do the caches remain synchronized? (and is this something that makes a non-trivial difference to performance?)
vincom2
google "MESI protocol"
kayvonf
@PID_1. Great question. This will be the topic of two lectures on cache coherence coming up in class.
How does hardware avoid this problem at the cache level. For example, if two processors both have the same memory address in their L1 cache and are reading from and writing to it concurrently, how do the caches remain synchronized? (and is this something that makes a non-trivial difference to performance?)
google "MESI protocol"
@PID_1. Great question. This will be the topic of two lectures on cache coherence coming up in class.