I'm having a bit of trouble understanding communication misses. Is the miss similar to the other types in that the data is not in the cache? How can communication misses be reduced or avoided?

A communication miss occurs when some data is loaded into some cache, but is loaded into the wrong cache (e.g. on a different processor or across the network). So we are forced to incur the cost of communicating the data.

(For reducing communication: See slide 44)

Computer architects often refer to communication misses as coherence misses. We'll see more on this topic in a few weeks, which should cover more of how communication results in cache misses.

If I'm understanding this correctly, a communication miss occurs when the state of your cache is inconsistent (not up-to-date) with the actual state of the backing memory. This will occur when another processor is writing to memory in the same address as one that's in your cache.

@Elmur_Fudd, yes, you have given one of the scenarios of a communication / coherence miss, but there are others.