Does registers in the processor affect the protocol?
mperron
@bojianh As I understand it, the compiler can decide which variables are shared and not assign those to registers. For example, variables local to a function often need not be written to memory, but can be stored in registers only. However if you are writing to the heap where another thread might see your changes, then after you make an operation you do a store in memory which triggers the protocols discussed .
aeu
Does L1 inform L2 of updates to a particular line in order for L2 to set its "modified-but-stale" it?
bpr
@aeu, it is probably handled in a simpler manner than informing of every update. The L2 could treat any cache line that is modified and in the L1 as "modified-but-stale". With high accuracy this is correct, and it simplifies the logic required.
yikesaiting
I am just thinking about what will happen when there are three layers of caches. In order to flush from L3, it will require L3 to have a bit for modified but stale state. However, it means when processor writes to L1, it will also writes to L2 and L3 cache. Would it be a little to expensive?
Does registers in the processor affect the protocol?
@bojianh As I understand it, the compiler can decide which variables are shared and not assign those to registers. For example, variables local to a function often need not be written to memory, but can be stored in registers only. However if you are writing to the heap where another thread might see your changes, then after you make an operation you do a store in memory which triggers the protocols discussed .
Does L1 inform L2 of updates to a particular line in order for L2 to set its "modified-but-stale" it?
@aeu, it is probably handled in a simpler manner than informing of every update. The L2 could treat any cache line that is modified and in the L1 as "modified-but-stale". With high accuracy this is correct, and it simplifies the logic required.
I am just thinking about what will happen when there are three layers of caches. In order to flush from L3, it will require L3 to have a bit for modified but stale state. However, it means when processor writes to L1, it will also writes to L2 and L3 cache. Would it be a little to expensive?