Why is this only true if L2 is larger than L1? If L2 is the same size as L1, and the processor accesses A many times which all hit in L1, when the processor accesses C, wouldn't L1 still evict A and L2 still evict B?
@huehue Sure. If L1 and L2 have the same size, this issue should still occur. The point that Kayvon was making on this slide is just that having a larger L2 cache than an L1 cache does not necessarily imply inclusion, as shown by the example above.
Yeah, when he asked this question, he was trying to see if we would think that a bigger L2 cache meant that the L1 cache would always be a strict subset of the L2 cache. (which it's not evidently haha)
Here the LRU policy on L1 doesn't apply to L2, so the L1 and L2 aren't necessary consistent.
A solution to this would be to have a bit indicating if the element is in L1 also.