What does "modified-but-stale" mean and how doe sit help with maintaining inclusion?
mperron
@TomoA Modified but stale means that the data is in L1 and has been modified, this means if we have to evict and flush to memory, we have to ask the L1 for the most current data before flushing. This is different than "in L1" because L1 might only be reading the data and we don't have to ask the L1 cache before flushing to memory.
BensonQiu
When the processor writes to L1 (write hit), L1 will always communicate to L2 so that L2 knows to set the "modified-but-stale" bit. L1 knows that it always needs to do this because everything in L1 is also in L2 by the inclusion property. Is this the right idea?
Hil
I think here adding a bit is more efficient than updating L2 cache line immediately because firstly updating a bit is faster than updating whole cache line and secondly processor may write to a line several times before it is flushed.
qqkk
Modified (in L1) but stale (in L2).
When a bus read come requesting L2 to get the data, L2 need to fetch modified data from L1 first.
When L1 write hit happens, why can't L1 just flush data to L2?Is it because in that case it breaks write-back policy?
What does "modified-but-stale" mean and how doe sit help with maintaining inclusion?
@TomoA Modified but stale means that the data is in L1 and has been modified, this means if we have to evict and flush to memory, we have to ask the L1 for the most current data before flushing. This is different than "in L1" because L1 might only be reading the data and we don't have to ask the L1 cache before flushing to memory.
When the processor writes to L1 (write hit), L1 will always communicate to L2 so that L2 knows to set the "modified-but-stale" bit. L1 knows that it always needs to do this because everything in L1 is also in L2 by the inclusion property. Is this the right idea?
I think here adding a bit is more efficient than updating L2 cache line immediately because firstly updating a bit is faster than updating whole cache line and secondly processor may write to a line several times before it is flushed.
Modified (in L1) but stale (in L2). When a bus read come requesting L2 to get the data, L2 need to fetch modified data from L1 first.
When L1 write hit happens, why can't L1 just flush data to L2?Is it because in that case it breaks write-back policy?