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These concepts look pretty much like blocking and I/O multiplexing except that the implementation on hardware is a lot more complex.


This reminds me about latency-hiding - while the memory is fetching some data, we do other operations on the bus.

A question about memory: The slide states "Memory gains access to bus". (Also, in slide 66, memory competes for bus.)So far, it seemed like whenever the memory was ready to send out the data to respond to a request it would do so immediately. Does this statement imply that memory competes with caches for bus access? How does this affect memory latency?


Why does the different possible timelines not affect correctness of a program?


@eknight7 Yes, memory must also compete for access with the bus, because it is shared among all caches and main memory, and is how they communicate. This will naturally increase latency, since this adds another contender to the bus.

@grarawr Well the different possible timelines can affect the correctness of a program, at least if it multi-threaded. If the program is single-threaded, then obviously the bus timeline is irrelevant, because all data is private to program.

In the multi-threaded program, the different timelines may affect the correctness of the program, which is why synchronization is required. This is elaborated more on in the memory consistency lecture.