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eknight7

Sorry, whats ASM here?

althalus

@eknight, I believe it means in assembly language.

xingdaz

Here is a case of cmpxchg in action trying to acquire a lock to a piece of CMOS memory. More detail here http://heather.cs.ucdavis.edu/~matloff/50/PLN/lock.pdf. The CPU reads the lock value into ?x and test if it is zero. And then use lock cmpxchg cmos_lock ?x to try to acquire the lock. Lastly, it checks ?x again to see if other CPU has beaten it to locking it.

Josephus

To implement compare-and-swap (assuming EBX has b, ECX has a, and EDX has x):

casBool:

mov eax, ecx

lock cmpxchg [edx], ebx

bnz casFalse

mov eax, 1

ret


casFalse:

mov eax, 0

ret

cyl

Whats the differece between cmpxchg ans ts? From my understanding, the differences is ts can only update the memory to 0 and 1, while cmpxchg can set the memory to arbitrary value.

trappedin418

I'm not sure if this applies here but TS counts as a write, whether it actually writes or not. This is the core issue behind the cache coherence traffic.

IF compare-and-swap DOESN'T cause a cache invalidation on failed write (only a read), then it does NOT invalidate the cache line and does not cause the line to rapidly switch between processors. I'm not entirely sure if this actually possible to implement though since I recall that compare-and-swap is implemented WITH cache coherence.

EDIT: I think the idea of not causing a write if we just read and fail is the idea behind test-test-set in the following slides.