I didn't quite understand what the non-core space was during lecture.
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So in the case of Apple A9, the remaining non-core space is known to occupy the SRAM Cache Memory, 2 instances of SDRAM interface to connect to DRAMs. A multi-core on chip GPU so as to support the intensive graphic requirements for the phones etc. A GPU Shared Digital Logic and GPU Cache also is located on the same chip between the GPU Cores. A few things like Digital PLL are estimated to be there based on the functionality but have not been exactly located on the layout of the chip. Apart from this, the L1 and L2 Caches are also part of the chip. A Camera interface to interface directly to the camera sensor is also placed. These are some of the main non-core components in case of Apple A9 Chip. Approximately 33% of the chip would be the interconnect logic, routing paths, on chip sensors ( fabrication permitting ) to ensure that all these functionalities are correctly connected together and perform the task they are expected to when requested. Similar functionalities and designs are seen in standard flagship mobile and handheld devices.
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In case of the Intel Xeon Phi "Knights Landing" 72 Core CPU. There are 72 cores. So most of the chip area is occupied by these 72 cores. A huge server level cache of approximately 20MB is located on chip.
So the chips 72 core is made up of 36 Tiles interconnected by 2D Mesh. So these tiles consist of
2 Cores + 2 VPU/core ( Vector Processing Units) + 1 MB L2 Cache betweent the Core. There is an
MCDRAM: 16 GB (on-package Note: NOT on the chip) to provide a High BW. DDR4 Interface: 6 channels @ 2400 to support up to 384GB. There are IO interfaces: 36 lanes PCIe Gen3. 4 lanes of DMI for chipset. A single socket Node. Also there is a huge interconnect fabric which is called as OmniPath Architecture, which routes all around the chip. It is one of the established architectures along with the Infiniband architecture. You can read further about it here.
I didn't quite understand what the non-core space was during lecture.
So in the case of Apple A9, the remaining non-core space is known to occupy the SRAM Cache Memory, 2 instances of SDRAM interface to connect to DRAMs. A multi-core on chip GPU so as to support the intensive graphic requirements for the phones etc. A GPU Shared Digital Logic and GPU Cache also is located on the same chip between the GPU Cores. A few things like Digital PLL are estimated to be there based on the functionality but have not been exactly located on the layout of the chip. Apart from this, the L1 and L2 Caches are also part of the chip. A Camera interface to interface directly to the camera sensor is also placed. These are some of the main non-core components in case of Apple A9 Chip. Approximately 33% of the chip would be the interconnect logic, routing paths, on chip sensors ( fabrication permitting ) to ensure that all these functionalities are correctly connected together and perform the task they are expected to when requested. Similar functionalities and designs are seen in standard flagship mobile and handheld devices.
In case of the Intel Xeon Phi "Knights Landing" 72 Core CPU. There are 72 cores. So most of the chip area is occupied by these 72 cores. A huge server level cache of approximately 20MB is located on chip.
So the chips 72 core is made up of 36 Tiles interconnected by 2D Mesh. So these tiles consist of 2 Cores + 2 VPU/core ( Vector Processing Units) + 1 MB L2 Cache betweent the Core. There is an MCDRAM: 16 GB (on-package Note: NOT on the chip) to provide a High BW. DDR4 Interface: 6 channels @ 2400 to support up to 384GB. There are IO interfaces: 36 lanes PCIe Gen3. 4 lanes of DMI for chipset. A single socket Node. Also there is a huge interconnect fabric which is called as OmniPath Architecture, which routes all around the chip. It is one of the established architectures along with the Infiniband architecture. You can read further about it here.
https://www.hpcwire.com/2016/04/12/interconnect-offloading-versus-onloading/
This is usually the architecture found in Server Chips.