It exploits multiple parallel cores and needs to replicate all the instructions.
It relies on software (pThread, for example) to create threads.
SIMD parallelism.
It uses multiple ALUs to process the same instruction stream.
It happens in core and is the most efficient one that provides high throughput.
It is heavily used in graphics and complicated machine learning tasks.
Superscalar parallelism.
It depends on the hardware to automatically find out some instructions with no dependency of others in a single instruction stream that could be executed at the same time.
RomanArena
Also in the Assignment 1 we can see that several forms can be combined together to improve the performance, like SIMD and multi-core,which takes advantage of both vectorization and multi-core processing.
pk267
Q: What is the difference between Pipelining and Superscalar execution? Both of them seem to execute more than 1 instruction in any given clock cycle.
A: Dividing an instruction into 5 steps: IF, ID, EX, MEM and WB (notation from Patterson book) and executing one phase in each cycle is Pipelining. At any given clock cycle, more than 1 instruction is in the pipeline. But in each stage, there is just one instruction.
In Superscalar execution, there is more than 1 instruction in the, say, IF unit itself.
So, Pipelining would be something like:
IF\n
\t ID
\t\t EX
\t\t\t MEM
\t\t\t\t WB
Then, superscalar will be:
IF\n
IF\n
\t ID
\t ID
.
.
. and so on.
Also in the Assignment 1 we can see that several forms can be combined together to improve the performance, like SIMD and multi-core,which takes advantage of both vectorization and multi-core processing.
Q: What is the difference between Pipelining and Superscalar execution? Both of them seem to execute more than 1 instruction in any given clock cycle.
A: Dividing an instruction into 5 steps: IF, ID, EX, MEM and WB (notation from Patterson book) and executing one phase in each cycle is Pipelining. At any given clock cycle, more than 1 instruction is in the pipeline. But in each stage, there is just one instruction.
In Superscalar execution, there is more than 1 instruction in the, say, IF unit itself.
So, Pipelining would be something like:
IF\n \t ID \t\t EX \t\t\t MEM \t\t\t\t WB Then, superscalar will be: IF\n IF\n \t ID \t ID
. . . and so on.