In class we talked about which bits from the address form the tag. In this example, with a 64-byte cache line, the low-order six bits identify the byte in the block. If this is associative cache with S sets, then the next lg(S) bits of the address identify the set. The remaining (high order) bits of the address specify at the tag, which is used to identify if the line is present in the appropriate set.
Why are the tag bits the high order bits? Because it makes sense that as we move through the address space we walk across the sets of the cache. Consider the case of a direct mapped cache. We'd like consecutive bytes in the address space to fit in cache at the same time, so the middle bits determine the set. Only after moving an entire cache size number of bytes in the address space do we encounter conflicting addresses.
So the mapping of bits in the address to cache lookup parameters is: [TAG | SET | BLOCK].
I don't think I answered this question very clearly in class, so I wanted to clarify here.
pdp
In a direct mapped cache, first the set bits are looked at which identifies which set in the cache to access, then the tag bits are compared to identify if the needed address is present in the cache, if so, the block offset is used to locate the specific byte location in the cache line.
In a set-associative cache, the set bits identify the set, then the tag bits are compared in parallel across all cache lines in that particular set, the block bits then provide the byte offset needed.
In both these cases, we want adjacent memory locations to map onto different sets and choosing the middle bits for set identification helps in that regard.
1_1
If this were a write-through cache, the write could have gone straight out to memory without impacting the cache at all, but then you're not making use of the cache.
In class we talked about which bits from the address form the tag. In this example, with a 64-byte cache line, the low-order six bits identify the byte in the block. If this is associative cache with S sets, then the next lg(S) bits of the address identify the set. The remaining (high order) bits of the address specify at the tag, which is used to identify if the line is present in the appropriate set.
Why are the tag bits the high order bits? Because it makes sense that as we move through the address space we walk across the sets of the cache. Consider the case of a direct mapped cache. We'd like consecutive bytes in the address space to fit in cache at the same time, so the middle bits determine the set. Only after moving an entire cache size number of bytes in the address space do we encounter conflicting addresses.
So the mapping of bits in the address to cache lookup parameters is:
[TAG | SET | BLOCK].I don't think I answered this question very clearly in class, so I wanted to clarify here.
In a direct mapped cache, first the set bits are looked at which identifies which set in the cache to access, then the tag bits are compared to identify if the needed address is present in the cache, if so, the block offset is used to locate the specific byte location in the cache line.
In a set-associative cache, the set bits identify the set, then the tag bits are compared in parallel across all cache lines in that particular set, the block bits then provide the byte offset needed.
In both these cases, we want adjacent memory locations to map onto different sets and choosing the middle bits for set identification helps in that regard.
If this were a write-through cache, the write could have gone straight out to memory without impacting the cache at all, but then you're not making use of the cache.