How to define "sufficiently separated" here? What if in a particular process the read and write need a very long time to fulfill condition 2? What is the influence?
shhhh
I would also like clarification on "sufficiently separated". Is a memory system still coherent if a read by P1 immediately following a write by P2 returns a different value (since there is essentially no time in between).
rc0303
@shhhh It seems like it depends on the coherence implementation used, so "sufficiently separated" should mean long enough for P2's cache to communicate the fact that there was a write to P1's cache. If P1 reads before that information is communicated, then the system is still coherent as long as all processors "observe" the same order, though I am not clear on what "observe" really means.
nemo
Can anybody give an example of a situation when the first two are satisfied and the third one is not? Will help in better understanding.
rootB
@nemo Assume P1 writes X=1, and P2 writes X=2, P3 and P4 read X after the writes. A read by P1 some sufficient time after P1 writes gets X=1, and a read by P2 some sufficient time after P2 writes gets X=2(satisfies the first condition). P3 and P4 both successfully got notified about both stores (satisfies the second condition), but P3 thinks X=1 came before X=2, p4 thinks X=2 came before X=1 (violates the third condition).
How to define "sufficiently separated" here? What if in a particular process the read and write need a very long time to fulfill condition 2? What is the influence?
I would also like clarification on "sufficiently separated". Is a memory system still coherent if a read by P1 immediately following a write by P2 returns a different value (since there is essentially no time in between).
@shhhh It seems like it depends on the coherence implementation used, so "sufficiently separated" should mean long enough for P2's cache to communicate the fact that there was a write to P1's cache. If P1 reads before that information is communicated, then the system is still coherent as long as all processors "observe" the same order, though I am not clear on what "observe" really means.
Can anybody give an example of a situation when the first two are satisfied and the third one is not? Will help in better understanding.
@nemo Assume P1 writes X=1, and P2 writes X=2, P3 and P4 read X after the writes. A read by P1 some sufficient time after P1 writes gets X=1, and a read by P2 some sufficient time after P2 writes gets X=2(satisfies the first condition). P3 and P4 both successfully got notified about both stores (satisfies the second condition), but P3 thinks X=1 came before X=2, p4 thinks X=2 came before X=1 (violates the third condition).