Each cache line in each processor's cache has its own state. For each PrRd and PrWr, it must check the states of same line from other caches with BusRd or BusRdX to check whether it can perform the operation.
Each cache line in each processor's cache has its own state. For each PrRd and PrWr, it must check the states of same line from other caches with BusRd or BusRdX to check whether it can perform the operation.