MESI improves upon MSI by having a separate state for when a cache line is only owned by one processor, but unmodified. Any modifications to this cache line don't require a bus write so it lowers the amount of communication across the bus.
kayvonf
Question: As @lilli says, why is no additional inter-cache communication necessary to move a line in the local cache from the E (exclusive clean) to M (exclusive for modification) state?
mumen_rider
If a line in the local cache is in the E state then this implies that this line in all other caches is invalid. So if we move this line to the M state no other caches "care" about the line and thus we don't need to send any bus messages.
cluo1
When there is a read on the cache line and it's cache miss, how would it know which state to become? Exclusive or shared?
lilli
I feel like it should start off shared, because if it is exclusive then a read would invalidate the line in other caches. It could always be updated to exclusive later.
ggm8
@cluo1 I believe if P0 takes a cache miss on a read, a BusRd is sent out to all other cache controllers, and if P0 receives an assertion of Shared by another cache (because they have the line too), then the line is in Shared. If no such assertion is received, P0 can move the line directly into the Exclusive state.
lfragago
One important point is that whenever a processor has a cache MISS and other processors have the line in the shared (S) state, then the MESI protocol doesn't specify whether Memory or other processor having the line is responsible of bringing it to the processor cache.
The MESIF protocol, on the other hand delegates responsibility to a given processor to share that line.
MESI improves upon MSI by having a separate state for when a cache line is only owned by one processor, but unmodified. Any modifications to this cache line don't require a bus write so it lowers the amount of communication across the bus.
Question: As @lilli says, why is no additional inter-cache communication necessary to move a line in the local cache from the E (exclusive clean) to M (exclusive for modification) state?
If a line in the local cache is in the E state then this implies that this line in all other caches is invalid. So if we move this line to the M state no other caches "care" about the line and thus we don't need to send any bus messages.
When there is a read on the cache line and it's cache miss, how would it know which state to become? Exclusive or shared?
I feel like it should start off shared, because if it is exclusive then a read would invalidate the line in other caches. It could always be updated to exclusive later.
@cluo1 I believe if P0 takes a cache miss on a read, a BusRd is sent out to all other cache controllers, and if P0 receives an assertion of Shared by another cache (because they have the line too), then the line is in Shared. If no such assertion is received, P0 can move the line directly into the Exclusive state.
One important point is that whenever a processor has a cache MISS and other processors have the line in the shared (S) state, then the MESI protocol doesn't specify whether Memory or other processor having the line is responsible of bringing it to the processor cache.
The MESIF protocol, on the other hand delegates responsibility to a given processor to share that line.