There is no invalid state here as PrWr by a processor also involves a BusUpd, which means that at no point in time any processor will have an invalid value. They get the updated value through the interconnect as soon as it written. The state when the line is not in cache can be thought of as invalid. That is where the horizontal arrows in the four corners would originate from!
Bye
Under what situation could PrWr/BusUpd happen from SM to M (also from SC to M)? SM defines the sharing status and it transits to M only when there is no other sharing, which kind of conflicts the definition of Shared-Modified.
My guess is that in SM or SC, the cache controller does not detect "exclusive" modified status automatically when other processors no longer share the data, until a PrWr is issued on this processor. And this reduces the cost of update. Is that correct?
lya
@Bye Agree. Another example is that E to SC is triggered when a BusRd happens, which means there is another processor reading the data. However, after that, SC will never be transferred back to E even if other processors no longer share the cache line (e.g. due to eviction) and it is actually "exclusively" reading the line. The reason is that PrRd never checks sharing according to the figure.
There is no invalid state here as PrWr by a processor also involves a BusUpd, which means that at no point in time any processor will have an invalid value. They get the updated value through the interconnect as soon as it written. The state when the line is not in cache can be thought of as invalid. That is where the horizontal arrows in the four corners would originate from!
Under what situation could PrWr/BusUpd happen from SM to M (also from SC to M)? SM defines the sharing status and it transits to M only when there is no other sharing, which kind of conflicts the definition of Shared-Modified.
My guess is that in SM or SC, the cache controller does not detect "exclusive" modified status automatically when other processors no longer share the data, until a PrWr is issued on this processor. And this reduces the cost of update. Is that correct?
@Bye Agree. Another example is that E to SC is triggered when a BusRd happens, which means there is another processor reading the data. However, after that, SC will never be transferred back to E even if other processors no longer share the cache line (e.g. due to eviction) and it is actually "exclusively" reading the line. The reason is that PrRd never checks sharing according to the figure.