What do we mean by eventually propagate to other processors?
harlenVII
Dirty data may be put into write back buffer instead of directly writing back to memory. It's only guaranteed that the value will be written back eventually.
sandeep6189
@kapalani I think "eventually" is nothing but some duration(ideally very very very small) of time after which the value at an address X will be seen be as same by each processors.
shhhh
Could someone explain the difference to me again because I'm not sure I fully understand this. Does memory coherence encompass memory consistency?
Brandon
That seems like a reasonable conclusion - coherence says somewhat strongly that there is a single unified timeline for an address X that is consistent with all processors. Where as consistency says that that timeline will guarantee that a write to X will be apparent to a later read eventually. That is to say that if you have a promise of consistency you do not necessarily have such a timeline as a read after another processors write may or may not be apparent yet, however in the reverse such a timeline should ensure that this write is apparent.
What do we mean by eventually propagate to other processors?
Dirty data may be put into write back buffer instead of directly writing back to memory. It's only guaranteed that the value will be written back eventually.
@kapalani I think "eventually" is nothing but some duration(ideally very very very small) of time after which the value at an address X will be seen be as same by each processors.
Could someone explain the difference to me again because I'm not sure I fully understand this. Does memory coherence encompass memory consistency?
That seems like a reasonable conclusion - coherence says somewhat strongly that there is a single unified timeline for an address X that is consistent with all processors. Where as consistency says that that timeline will guarantee that a write to X will be apparent to a later read eventually. That is to say that if you have a promise of consistency you do not necessarily have such a timeline as a read after another processors write may or may not be apparent yet, however in the reverse such a timeline should ensure that this write is apparent.