Could someone help elaborate on the details about what will happen when the L2 missed? Here is what I got from the lecture: when L2 miss, it goes to some directory, and it asked L3 who's the sharers.
nemo
@cwchang That's right! Let's consider each case separately -
For read miss in L2 (let's say first L2 cache):
If L3 doesn't have the line, L3 gets the line and it is marked in the directory that first L2 is the sole sharer (L2 gets the line)!
If the entry already exists and dirty bit is off, directory is updated to reflect that now first L2 is also a sharer (L2 gets the line).
If the entry already exists and dirty bit is on, first L2 gets the owner's ID. It asks the owner L2 to send the line. The owner sends the line to first L2 and the directory (now updated with the new value). Dirty bit is turned off.
For write miss in first L2:
If L3 does not have the line, L3 gets the line, sends it to first L2 and it is marked in the directory that first L2 has it and the dirty bit is turned on! (no sharer list)
If the entry already exists and dirty bit is off, line is sent to first L2 with the sharer's lists, directory is updated to reflect that now first L2 has the line, dirty bit is turned on. First L2 will send messages to relevant L2s to invalidate their line and will update the value (after getting acks).
If the entry already exists and dirty bit is on, first L2 gets the owner's ID, it asks the owner L2 to send the data and invalidate its entry. The owner sends the line to first L2 and invalidates its own line. Directory is updated to reflect that only first L2 has the line (dirty bit still on) (Note: There are multiple ways this communication can happen as we have seen)
hzxa21
Can someone help to explain what ring interconnect is? I am still confused even after reading some relevant articles. Does it mean that there exist independent links between each pair of the L2 caches?
rsvaidya
@hzxa21 Ring interconnect is when the caches are connected to two caches, one on each side. And also it is in circle i.e. the last cache is connected to the first one and the second last one.
Could someone help elaborate on the details about what will happen when the L2 missed? Here is what I got from the lecture: when L2 miss, it goes to some directory, and it asked L3 who's the sharers.
@cwchang That's right! Let's consider each case separately -
For read miss in L2 (let's say first L2 cache):
For write miss in first L2:
Can someone help to explain what ring interconnect is? I am still confused even after reading some relevant articles. Does it mean that there exist independent links between each pair of the L2 caches?
@hzxa21 Ring interconnect is when the caches are connected to two caches, one on each side. And also it is in circle i.e. the last cache is connected to the first one and the second last one.