In this case, since no switches are added, I think the cost would be O(1) and also since this follows a broadcast mechanism for communication, latency would also be O(1). Please correct me, if am wrong.
vasua
Many embedded systems also use some sort of bus design due to its simplicity. For example, CAN, I2C, SPI are all rather common interconnect networks for various embedded processors, sensors, etc, and are all a bus (with varying numbers of wires).
shreeduh
I think it isn't directly possible to quantify latency here ,in terms of number of switch hops like other networks. Latency here would be decided by the bandwidth and bus contention, and under worst-case contention, could lead to O(N) latency : N is number of nodes on bus.
In this case, since no switches are added, I think the cost would be O(1) and also since this follows a broadcast mechanism for communication, latency would also be O(1). Please correct me, if am wrong.
Many embedded systems also use some sort of bus design due to its simplicity. For example, CAN, I2C, SPI are all rather common interconnect networks for various embedded processors, sensors, etc, and are all a bus (with varying numbers of wires).
I think it isn't directly possible to quantify latency here ,in terms of number of switch hops like other networks. Latency here would be decided by the bandwidth and bus contention, and under worst-case contention, could lead to O(N) latency : N is number of nodes on bus.