The topology suggest that every two cores share an L2 cache.
Messages are routed horizontally first, then vertically for this chip
I wonder what the reason for routing horizontally first and then vertically? Is it better performance, and if so why?
Should YX routing mean that messages are routed vertically first, then horizontally?
The topology suggest that every two cores share an L2 cache.
Messages are routed horizontally first, then vertically for this chip
I wonder what the reason for routing horizontally first and then vertically? Is it better performance, and if so why?
Should YX routing mean that messages are routed vertically first, then horizontally?