Are "double compare-and-swap" instructions commonly available on other instruction sets?
zale
@holard Proper double compare-and-swap can be implemented on top of transactional memory fairly easily (just do two reads and a write in a transaction). Some architectures, like recent versions of Power and some rare versions of x86 support it. DCAS was apparently supported on some m68k processors as well.
I wouldn't be surprised if double-width compare-and-swap was much more widely available, and it seems the problem can generally be solved using it. On 64-bit architectures, it is probably often possible to do what you want using two 32-bit values and using a regular 64-bit compare-and-swap as a poor man's DWCAS.
Are "double compare-and-swap" instructions commonly available on other instruction sets?
@holard Proper double compare-and-swap can be implemented on top of transactional memory fairly easily (just do two reads and a write in a transaction). Some architectures, like recent versions of Power and some rare versions of x86 support it. DCAS was apparently supported on some m68k processors as well.
I wouldn't be surprised if double-width compare-and-swap was much more widely available, and it seems the problem can generally be solved using it. On 64-bit architectures, it is probably often possible to do what you want using two 32-bit values and using a regular 64-bit compare-and-swap as a poor man's DWCAS.